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| Signal Integrity in Printed Circuit Boards | |
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High speed digital design on printed circuit boards requires analysis of the layout. CAE tools assist with this high-speed board layout analysis. Most boards are built without analysis of the signal integrity. Instead, experienced engineers carefully apply the lessons that they have learned in each design that they do. When there are problems with signal integrity, the emphasis is usually on how fast another design iteration can be performed.
Inexperienced engineers are the best customers for signal integrity tools, since they can get some experience through virtual prototyping. Other customers are more experienced designers that are in a hurry to learn the requirements for a new technology. For example, when Pentium chips came to market it was extrodinarily difficult for designers to get the part to work, because the parts had faster risetimes than previous digital parts. Still, the amazing thing about any signal integrity software is that it works at all, not how well it works. The tools are not for the feint of heart.
Although clock speeds are often named as a source of problems, it is actually risetime that causes the trouble. Faster clock speeds tend to be associated with faster risetimes, though.
The more common usage of signal integrity tools is in IC design. These tools for the most part can ignore the effects of inductance. You can tell when an IC designer discovers inductance. "The signal level is higher than the supply! How is this possible?" she asks.
Inductance causes problems that capacitance does not during parasitic extraction and simulation. One problem is that it is easy to describe a system of coupled inductors that will generate energy all by itself. Since interconnect systems do not normally generate their own energy, this causes a simulation error that can grow in magnitude as the simulation progresses. In other words, simulations tend to blow up. This is why most simulators do not really account for inductive coupling between traces (even when they claim that they do.) It is not uncommon for a simulator to have a switch that allows you to turn on the inductive coupling effect. The tool users then fastidiously avoid the inductive coupling feature, which breaks the simulation.
If inductive coupling were not important, this wouldn't be a problem. Unfortunately, inductive coupling is one of the two or three worst problems in signal integrity. Some tools just calculate 'crosstalk,' which should in theory account for inductive coupling. It might, or it might not, depending on your layout and the approximation technique. In the boards that I have designed, I want to look at simulated waveforms, not a guestimated table of noise margins.
If someone has a product that can predict a coupled waveform, I would be glad to try it. I have built and measured some test boards, so I am qualified to try it. I have access to the best test equipment. Send email to sigint@tomacorp.com and tell me what you've got!
| Quad Design/Viewlogic/Innoveda |
Innoveda Signal Integrity Products
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| Hyperlynx | HyperLynx, Inc. Home Page --- Hijacks the browser, last I tried this link! |
| CCT/Cadence | Specctraquest High-Speed Interconnect |
| Zuken/Incases | INCASES Signal Integrity Tools |
| Mentor/Interconnectix/Veribest | Interconnect Synthesis Interconnectix |
| Avant! |
Home Page They have a 2D EM simulator that is used to extract HSPICE models. |
| Quantic | Greenfield and other signal integrity tools |
| Ansoft | Brochure for Ansoft Signal Integrity Tools |
| Protel | Integrated signal integrity tools |
| GNU EDA | GPL Electronic Design Automation ... I haven't found a signal integrity tool from them yet. |